1. Technical Field
Exemplary embodiments of the inventive concept relate to a delay locked loop circuit, and more particularly, to a delay locked loop circuit to detect an operation error of a corresponding duty cycle correcting block and a semiconductor memory device including the same.
2. Discussion of Related Art
A clock signal may be used as a reference signal in electronic systems or circuits to synchronize the processing of operations according to a desired schedule. However, the internal circuitry of a semiconductor device may introduce a time delay into a clock signal input externally, thereby causing a clock skew. A delay locked loop circuit may be used to compensate for the time delay to ensure that the internal clock signal and the external clock signal have the same phase.
In the operation of certain semiconductor circuits, maintaining the duty ratio of the rising period to the falling period of the clock may have a higher priority than ensuring that the delay of the clock be locked to a particular delay value. Accordingly, certain semiconductor circuits may include a duty cycle correcting function.
However, even after a duty cycle correcting function is used, a duty correction error may be caused by a variation in process, voltage, and temperature (PVT), thereby resulting in a phase delay.
It is desirable that a correction circuit implementing the duty cycle correction be able to generate an internal clock having a constant duty ratio regardless of the duty ratio of an external clock. However, when the correction circuit is shorted to a ground voltage or a power supply voltage, it can be difficult to maintain an internal clock having a constant duty ratio.